Memory cells of a dynamic random access memory (DRAM) generally include a storage capacitor for storing an electrical charge which represents information to be stored, and an access transistor which is connected with the storage capacitor. The access transistor includes a first and a second source/drain regions, a channel connecting the first and the second source/drain regions as well as a gate electrode controlling an electrical current flow between the first and second source/drain regions. The transistor usually is at least partially formed in the semiconductor substrate. The gate electrode forms part of a word line and is electrically isolated from the channel by a gate dielectric. By addressing the access transistor via the corresponding word line, the information stored in the storage capacitor is read out.
In the currently used DRAM memory cells, the storage capacitor can be implemented as a trench capacitor in which the two capacitor electrodes are disposed in a trench which extends in the substrate in a direction perpendicular to the substrate surface.
According to another implementation of the DRAM memory cell, the electrical charge is stored in a stacked capacitor, which is formed above the surface of the substrate.
A memory device further includes a peripheral portion. Generally, the peripheral portion of the memory device includes circuitry for addressing the memory cells and for sensing and processing the signals received from the individual memory cells. Usually, the peripheral portion is formed in the same semiconductor substrate as the individual memory cells. Hence it is highly desirable to have a manufacturing process by which the components of the memory cell array and the peripheral portion can be formed simultaneously.
In the transistors of a memory cell, there is a lower boundary of the channel length of the transistor, below which the isolation properties of the access transistor in a non-addressed state are not sufficient. The lower boundary of the effective channel length leff limits the scalability of planar transistor cells having an access transistor which is horizontally formed with respect to the substrate surface of the semiconductor substrate.
Vertical transistor cells offer a possibility of enhancing a channel length while maintaining the surface area necessary for forming the memory cell. In such a vertical transistor cell the source/drain regions of the access transistor as well as the channel region are aligned in a direction perpendicular to the substrate surface.
A concept, in which the effective channel length Leff is enhanced, refers to a recessed channel transistor, as is for example known from U.S. Pat. No. 5,945,707. In such a transistor, the first and second source/drain regions are arranged in a horizontal plane parallel to the substrate surface. The gate electrode is arranged in a groove, which is formed in the semiconductor substrate. The groove is disposed between the two source/drain regions of the transistor. Accordingly, the effective channel length equals to the sum of the distance between the two-source/drain regions and the twofold of the depth of the recess groove. The effective channel width Weff corresponds to the minimal structural size F.
Another known transistor concept refers to the FinFET. The active area of a fin FET usually has a shape of a fin or a ridge which is formed in a semiconductor substrate between the two source/drain regions. A gate electrode encloses the fin at two or three sides thereof. “Fin-channel-array transistor (FCAT) featuring sub-70 nm low power and high performance DRAM” by Deok-Hyung Lee at al., IEDM Tech. Dig., pp. 407 to 410, 2003 discloses a further transistor.
A method of forming special contact plugs is described in U.S. patent application Ser. No. 2005/0003308, the contents thereof being incorporated herein in its entirety.